Field of the Invention
The present disclosure relates to a display device and a driving method thereof.
Discussion of the Related Art
There are various flat display devices including a Liquid Crystal Display (LCD) device and an Organic Light Emitting Diode (OLED) device. The LCD displays an image by controlling an electric field, applied to liquid molecules, according to a data voltage. In an active-matrix display device, each pixel includes a Thin Film Transistor (TFT) formed therein.
An active-matrix OLED device utilizes an Organic Light Emitting Diode (OLED) and thus exhibits fast response speed, great luminance, and a wide viewing angle. Each OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer consists of a Hole Injection layer (HIL), a Hole transport layer (HTL), an Emission layer (EML), an Electron transport layer (ETL), and an Electron Injection layer (EIL). Once a driving voltage is applied to the anode and the cathode, a hole passing through the HTL and an electron passing through the ETL move to the EML, and therefore, the EML generates a visible light accordingly.
Such a display device includes a plurality of source drive integrated circuits (ICs) for supplying a data voltage to data lines, a plurality of gate drive ICs for sequentially supply a gate pulse (or a scan pulse) to gate lines (or scan lines) of the display panel, and a timing controller for controlling the drive ICs.
Through an interface, such as a mini Low Voltage Differential Signaling (LVDS) interface, the timing controller supplies the source drive ICs with digital video data, a clock for sampling the digital video data, and a control signal for controlling operation of the source drive ICs. The source drive ICs convert digital video data, received from the timing controller, into an analog data voltage, and supply the analog data voltage to the data lines.
In a case the timing controller and the source drive ICs are connected in a multi-drop fashion via the mini LVDS interface, various and many lines are required: for example, an R data transmission line, a G data transmission line, a B data transmission line, and control lines for controlling the source drive ICs are necessary between the controller and the source drive ICs. In the case of transmission of RGB data via the mini LVDS interface, RGB digital video data and a clock are separately transmitted with a differential signal pair. In this case, for simultaneous transmission of odd-numbered data and even-numbered data, at least fourteen lines between the timing controller and the source drive ICs are required in order to transmit RGB data. If RGB data is 10 bits, eighteen lines are needed. Therefore, a lot of lines have to be formed on a source Printed Circuit Board (PCB) mounted between the timing controller and the source drive ICs, and thus, it is such a challenge to reduce the width of the source PCB.
The applicant of this application has proposed a new signal transmission protocol (hereinafter, referred to as “Embedded Panel Interface (EPI) protocol”) in Korean Patent Application No. 10-2008-0127458 (Dec. 15, 2008), U.S. patent Ser. No. 12/543,996 (Aug. 19, 2009), Korean Patent Application No. 10-2008-0127456 (Dec. 15, 2008), U.S. patent application Ser. No. 12/461,652 (Aug. 19, 2009), Korean Patent Application No. 10-2008-0132466 (Dec. 23, 2008), and U.S. patent application Ser. No. 12/537,341 (Aug. 7, 2009). The EPI protocol is for connecting a timing controller and source drive ICs in a point-to-point manner so as to minimize the number of lines necessary between the timing controller and the source drive ICs and stabilize signal transmission.
The EPI protocol satisfies interface requirements (1) to (3) as below.
(1) A transmitting end of the timing controller and receiving ends of the source drive ICs do not share a line and instead bypasses a data line pair which connects the transmitting end of the timing controller and the receiving ends of the source drive ICs in a point-to-point manner.
(2) The timing controller and the source drive ICs are not connected using an additional clock line pair. The timing controller transmits a clock signal, video data, and control data to the source drive ICs through the data line pair.
(3) A clock recovery circuit for Clock and Data Recovery (CDR) is embedded in each of the source drive ICs. In order to lock an output phase and a frequency of the clock recovery circuit, the timing controller transmits a clock training pattern signal (or a preamble) to a source to the source drive ICs. When the clock training pattern signal and a clock signal are input through a data line pair, clock recovery circuit embedded in each of the source drive ICs recovers the clock signal to generate an internal clock.
If the phase and frequency of the internal clock are locked, the source drive ICs inputs, to the timing controller, a lock signal LOCK at a high logic level which indicates a state of output stability. The lock signal LOCK is input to the timing controller along a lock feedback line that connects the timing controller and the last source drive IC.
According to the EPI protocol, as described above, the timing controller transmits a clock training pattern signal to the source drive ICs before transmitting control data and video data of an input image. A clock recovery circuit embedded in each of the source drive IC performs a clock training operation by outputs an internal clock with reference to the clock training pattern signal and then recovering a clock. If the phase and frequency of the internal clock is stably fixed, the clock recovery circuit establishes a data link with the timing controller. In response to a lock signal received from the last source drive IC, the controller starts to transmit the control data and the video data to the source drive ICs.
An LCD device processes a great volume of data at a high speed and data traffic load increases because a display panel has high resolution and a large screen. If the source drive ICs outputs data voltages at the same time when the data traffic load has increased, it may result in an increase in noise of electromagnetic interference (EMI) in a broadband. To reduce the EMI, an SOE Split scheme may be applied which is used to separate timings of Source Output Enable (SOE) signals. In the SOE Split scheme, output timings of the source drive ICs are disperse along the time axis to reduce the peak current of the source drive ICs. The SOE Split scheme renders delay time of each SOE signal different, the SOE signal which is for controlling an output timing of a source drive IC. The SOE Split scheme is disclosed in Korean Patent Application No. 10-2010-0073739 (Jul. 1, 2010), and Korean Patent No. 10-0880222 (Jan. 16, 2009), both of which are invented by the applicant of this application.
The conventional SOE Split scheme has to adjust a timing of an SOE signal at a predetermined tine interval. As the conventional SOE Split scheme splits a timing of the SOE signal at the predetermined time interval, the effects in reducing the peak current are limited. In addition, as the conventional SOE Split scheme splits a timing of the SOE signal at the predetermined time interval, the timing of SOE signals in a source drive IC or between source drive ICs may periodically overlap. As the conventional SOE Split scheme causes the timing of SOE signals in a source drive IC or between source drive ICs to overlap, there is an accumulated value of the peak current. The accumulated value of the peak current is hard to anticipate because propagation delay differs according to size and resolution of a display panel. Even when the same IC chip is used, a different level of EMI is found in each display panel model. Therefore, the conventional SOE Split Scheme has a limitation in reducing the EMI.